MPC8641D datasheet(8/140 Pages) FREESCALE

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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Electrical Characteristics

Local Bus and Platform PLL supply voltage

AVDD_LB,

AVDD_PLAT

1.10 ± 50 mV

1.05 ± 50 mV

DDR and DDR2 SDRAM I/O supply voltages

D1_GVDD,

D2_GVDD

2.5 V ± 125 mV

1.8 V ± 90 mV

eTSEC 1 and 2 I/O supply voltage

LVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

eTSEC 3 and 4 I/O supply voltage

TVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

Local Bus, DUART, DMA, Multiprocessor Interrupts, System

Control & Clocking, Debug, Test, Power management, I2C,

JTAG and Miscellaneous I/O voltage

OVDD

3.3 V ± 165 mV

Input voltage

DDR and DDR2 SDRAM signals

_MVIN

GND to D

n_GVDD

V3, 6

DDR and DDR2 SDRAM reference

_MV

REF

n_GVDD/2 ± 1%

Three-speed Ethernet signals

LVIN

TVIN

GND to LVDD

GND to TVDD

V4, 6

DUART, Local Bus, DMA,

Multiprocessor Interrupts, System

Control & Clocking, Debug, Test,

Power management, I2C, JTAG

and Miscellaneous I/O voltage

OVIN

GND to OVDD

V5,6

Junction temperature range

0 to 105

°C

Notes:

1. Core 1 characteristics apply only to MPC8641D

2. If two separate power supplies are used for VDD_Core0 and VDD_Core1, they must be at the same nominal voltage and the

individual power supplies must be tracked and kept within 100 mV of each other during normal run time.

3. Caution: D

_MVIN must meet the overshoot/undershoot requirements for Dn_GVDD as shown in Figure 2.

4. Caution: L/TVIN must meet the overshoot/undershoot requirements for L/TVDD as shown in Figure 2 during regular run time.

5. Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 2 during regular run time.

6. Timing limitations for M,L,T,O)VIN and Dn_MVREF during regular run time is provided in Figure 2

7. Applies to devices marked with a core frequency of 1333 MHz and below. Refer to Table 74 Part Numbering Nomenclature

to determine if the device has been marked for a core frequency of 1333 MHz and below.

8. Applies to devices marked with a core frequency above 1333 MHz. Refer to Table 74 Part Numbering Nomenclature to

determine if the device has been marked for a core frequency above 1333 MHz.

9. The 2.5 V ± 125 mV range is for DDR and 1.8 V ± 90 mV range is for DDR2.

10. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications” for details on the recommended

operating conditions per protocol.

11. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. For more information refer to

Section 14.4.3, “Differential Receiver (RX) Input Specifications."

12. Applies to Part Number MC8641xxx1000NX only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V devices. Refer to Table 74

Part Numbering Nomenclature to determine if the device has been marked for VDD_Coren = 0.95 V.

13. This voltage is the input to the filter discussed in Section 20.2, “Power Supply Design and Sequencing” and not necessarily

the voltage at the AVDD_Coren pin, which may be reduced from VDD_Coren by the filter.

Table 2. Recommended Operating Conditions (continued)

Characteristic

Symbol

Recommended

Value

Unit

Notes

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