TSA1001IFT datasheet(15/19 Pages) STMICROELECTRONICS

15 / 19 page

TSA1001

15/19

External reference

It is possible to use an external reference voltage

instead of the internal one for specific applications

requiring

even

better

linearity

enhanced

temperature behaviour. In this case, the amplitude

of the external voltage must be at least equal to

the

internal

one

(1.03V).

Using

the

STMicroelectronics Vref TS821 leads to optimum

performances when configured as shown on

Figure 8.

Figure 8 : External reference setting

At 15Msps sampling frequency, 1MHz input fre-

quency and -1dBFS amplitude signal, perfor-

mances can be improved of up to 2dBc on SFDR

and 0.3dB on SINAD. At 25Msps sampling fre-

quency, 1MHz input frequency and -1dBFS ampli-

tude signal, performances can be improved of up

to 1dBc on SFDR and 0.5dB on SINAD.

This can be very helpful for example for multichan-

nel application to keep a good matching among

the sampling frequency range.

Clock input

The quality of your converter is very dependant on

your clock input accuracy, in terms of aperture jit-

ter; the use of low jitter crystal controlled oscillator

is recommended.

The duty cycle must be between 45% and 55%.

The clock power supplies must be separated from

the ADC output ones to avoid digital noise modu-

lation at the output.

It is recommended to always keep the circuit

clocked, even at the lowest specified sampling

frequency of 0.5Msps, before applying the supply

voltages.

Power consumption optimization

The internal architecture of the TSA1001 enables

to optimize the power consumption according to

the sampling frequency of the application. For this

purpose, a resistor is placed between IPOL and

the analog Ground pins.

The TSA1001 will combine highest performances

and lowest consumption at 25Msps when Rpol is

equal to 25k

Ω.

At lower sampling frequency range (< 10Msps),

this value of resistor may be adjusted in order to

decrease

the

analog

current

without

any

degradation of dynamic performances.

As an example, 10mW total power consumption is

achieved at 5 Msps with Rpol equal to 390k

Ω.

The table below sums up the relevant data.

Total power consumption optimization

depending on Rpol value

Layout precautions

To use the ADC circuits in the best manner at high

frequencies, some precautions have to be taken

for power supplies:

- First of all, the implementation of 4 separate

proper supplies and ground planes (analog,

digital, internal and external buffer ones) on the

PCB

mandatory

for

high

speed

circuit

applications to provide low inductance and low

resistance common return.

The separation of the analog signal from the

digital part is essential to prevent noise from

coupling onto the input signal.

- Power supply bypass capacitors must be placed

as close as possible to the IC pins in order to

improve high frequency bypassing and reduce

harmonic distortion.

- Proper termination of all inputs and outputs must

be incorporated with output termination resistors;

then the amplifier load will be only resistive and

the stability of the amplifier will be improved. All

leads must be wide and as short as possible

especially for the analog input in order to decrease

parasitic capacitance and inductance.

- To keep the capacitive loading as low as

possible at digital outputs, short lead lengths of

routing are essential to minimize currents when

the output changes. To minimize this output

capacitance, buffers or latches close to the output

pins will relax this constraint.

- Choose component sizes as small as possible

(SMD).

Ω

TSA1001

VIN

VINB

VREFM

VREFP

external

reference

TS821

VCCA

330pF

470nF

10nF

Fs (Msps)

Rpol (

Ω)

390

Optimized

power (mW)

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