TSA1201IFT datasheet(13/20 Pages) STMICROELECTRONICS

13 / 20 page

TSA1201

13/20

Slew Rate Control (SRC)

When set to high level (VIH), all digital outputs

currents are limited to a clamp value so that digital

noise power is reduced to its minimum. Rise and

fall times just match 25MHz sampling rate

assuming the load capacitance on each digital

output remains below 10pF.

When set to low level (VIL), the maximum digital

output current increases so that rise and fall times

just match the 50MHz sampling rate assuming the

load capacitance on each digital output remains

below 10pF.

Out of Range (OR)

This function is implemented on the output stage

in order to set up an "Out of Range" flag whenever

the digital data is over the full scale range.

Typically, there is a detection of all the data being

at ’0’ or all the data being at ’1’. This ends up with

an output signal OR which is in low level state

(VOL) when the data stay within in the range, or in

high level state (VOH) when the data are out of the

range.

Data Ready (DR)

The Data Ready output is an image of the clock

being synchronized on the output data (D0 to

D11). This is a very helpful signal that simplifes

the

synchronization

the

measurement

equipment or the controling DSP.

As digital output, DR goes into high impedance

state when OEB is asserted to high level as

described in the timing diagram.

DRIVING THE ANALOG INPUT

Differential inputs

The TSA1201 has been designed to obtain

optimum performances when being differentially

driven. An RF transformer is a good way to

achieve such performances.

Figure 1 describes the schematics. The input

signal is fed to the primary of the transformer,

while the secondary drives both ADC inputs. The

common mode voltage of the ADC (INCM) is

connected to the center-tap of the secondary of

the transformer in order to bias the input signal

around this common voltage, internally set to

0.56V. It determines the DC component of the

analog signal. As being an high impedance input,

it acts as an I/O and can be externally driven to

adjust

this

component.

The

INCM

decoupled to maintain a low noise level on this

node. Our evaluation board is mounted with a 1:1

ADT1-1 transformer from Minicircuits. You might

also use a higher impedance ratio (1:2 or 1:4) to

reduce the driving requirement on the analog

signal source.

Each analog input can drive a 1Vpp amplitude

input signal, so the resultant differential amplitude

is 2Vpp.

Figure 1 : Differential input configuration

Single-ended input configuration

Some applications may require a single-ended

input.

This

easily

achieved

with

the

configuration

reported

Figure

for

AC-coupled input or on Figure 3 and 4 for a

DC-coupled input..

In the case of AC-coupled analog input, it is

recommended to connect the other analog input to

the common mode voltage of the circuit (INCM) so

as to properly bias the ADC. The INCM may

remain at the same internal level (0.56V) thus

driving only a 1Vpp input amplitude, or it must be

increased to 1V to drive a 2Vpp input amplitude.

Figure 2 : AC-coupled Single-ended input

In the case of DC-coupled analog input, Figure 3

shows the configuration for a 2Vpp input signal.

The DC component is driven by VREFP which is

connected to INCM and VINB and therefore

imposes its voltage. VREFM being connected to

ground, a dynamic of 2Vpp is achievable.

Figure 4 describes the configuration for a 1Vpp

analog signal. In this case, VREFM is connected

TSA1201

VIN

VINB

INCM

Ω

100pF

330pF

470nF

10nF

Analog source

1:1

ADT1-1

TSA1201

VIN

VINB

INCM

Ω

100nF

330pF

470nF

10nF

Signal source

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