TSA1204

2/20

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=10.5MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V

Tamb = 25°C (unless otherwise specified)

DYNAMIC CHARACTERISTICS

TIMING CHARACTERISTICS

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

SFDR

Spurious Free Dynamic Range

-81.5

-71.0

dBc

SNR

Signal to Noise Ratio

66.9

68.5

dB

THD

Total Harmonics Distortion

-80

-70

dBc

SINAD

Signal to Noise and Distortion Ratio

64.8

68

dB

ENOB

Effective Number of Bits

10.6

11.2

bits

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

FS

Sampling Frequency

0.5

20

MHz

DC

Clock Duty Cycle

45

50

55

%

TC1

Clock pulse width (high)

22.5

25

ns

TC2

Clock pulse width (low)

22.5

25

ns

Tod

Data Output Delay (Clock edge to Data Valid)

10pF load capacitance

9

ns

Tpd I

Data Pipeline delay for I channel

7

cycles

Tpd Q

Data Pipeline delay for Q channel

7.5

cycles

Ton

Falling edge of OEB to digital output valid data

1

ns

Toff

Rising edge of OEB to digital output tri-state

1

ns