50%

90%

0.1% of e dge a mplitude

10%

TEST WAVEFORM

Input

50

Ω

1k

Ω

10nF

10

µF

-5V

+5V

10nF

Output

50

Ω

10

µF

1k

Ω

EVALUATION CIRCUIT

As for any high frequency device, a few rules must

be observed when designing the PCB to get the best

performances from this high speed op amp.

From the most to the least important points :

• Each power supply lead has to be bypassed

to ground with a 10nF ceramic capacitor very

close to the device and a 10

µF tantalum ca-

pacitor.

• To provide low inductance and low resistance

common return, use a ground plane or com-

mon point return for power and signal.

• All leads must be wide and as short as possi-

ble especially for op amp inputs. This is in

order to decrease parasitic capacitance and

inductance.

• Use small resistor values to decrease time

constant with parasitic capacitance. Be aware

noise currents with high feedback resistor val-

ues.

• Choose component sizes as small aspossible

(SMD).

• On output, decrease capacitor load so as to

avoid circuit stability being degraded which

may cause oscillation. You can also add a

serial resistor in order to minimise its influ-

ence.

• One can add in parallel with feedbackresistor

optimize the settling time.

PRINTED CIRCUIT LAYOUT

TSH150

4/7