MPC8313VRGDF datasheet(14/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 11 provides the PLL lock times.

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface. Note that

DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.

6.1

DDR and DDR2 SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) when

GVDD(typ) = 1.8 V.

Time for the device to turn on POR configuration signal drivers with respect to

the negation of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary

clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.

2. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.

3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 11. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs—

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

1.7

1.9

I/O reference voltage

MVREF

0.49

× GVDD

0.51

× GVDD

I/O termination voltage

VTT

MVREF –0.04

MVREF + 0.04

Input high voltage

VIH

MVREF +0.125

GVDD +0.3

—

Input low voltage

VIL

–0.3

MVREF – 0.125

—

Output leakage current

IOZ

–9.9

9.9

μA4

Output high current (VOUT = 1.420 V)

IOH

–13.4

—

Output low current (VOUT = 0.280 V)

IOL

13.4

—

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

≤ VOUT ≤ GVDD.

Table 10. RESET Initialization Timing Specifications (continued)

Parameter/Condition

Min

Max

Unit

Notes

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