74HC_HCT02_3

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 — 18 September 2008

2 of 15

NXP Semiconductors

74HC02; 74HCT02

Quad 2-input NOR gate

4.

Functional diagram

5.

Pinning information

5.1 Pinning

5.2 Pin description

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

mna216

1A

1B

1Y

3

2

1

2A

2B

2Y

6

5

4

3A

3B

3Y

9

8

10

4A

4B

4Y

12

11

13

001aah084

2

1

3

5

4

≥1

6

≥1

8

10

≥1

9

11

13

≥1

12

mna215

A

B

Y

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as a

supply pin or input.

Fig 4.

Pin configuration DIP14, SO14 and (T)SSOP14

Fig 5.

Pin configuration DHVQFN14

02

1Y

1A

4Y

1B

4B

2Y

4A

2A

3Y

2B

3B

GND

3A

001aac919

1

2

3

4

5

6

7

8

10

9

12

11

14

13

001aac920

02

Transparent top view

2B

3B

2A

3Y

2Y

4A

1B

4B

1A

4Y

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

Table 2.

Pin description

Symbol

Pin

Description

1Y to 4Y

1, 4, 10, 13

data output

1A to 4A

2, 5, 8, 11

data input

1B to 4B

3, 6, 9,12

data input

GND

7

ground (0 V)

14

supply voltage