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TSH70CD 数据表(PDF) 20 Page - STMicroelectronics |
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TSH70CD 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 25 page ![]() TSH70, 71, 72, 73, 74, 75 20/25 Video Results: Precautions on asymmetrical supply operation: The TSH7X can be used either with a dual or a single supply. If a single supply is used, the inputs are biased to the mid-supply voltage (+Vcc/2). This bias network must be carefully designed, in order to reject any noise present on the supply rail. As the bias current is 15uA, you must carefully choose the resistance R1 not to introduce an off- set mismatch at the amplifier inputs. R1=10K Ω will be convenient. C1, C2, C3 are by- pass capacitors from perturbation on Vcc as well as for the input and output signals. We choose C1=100nF and C2=C3=100uF. R2, R3 are such that the current through them must be superior to 100 times the bias current. So, we take R2=R3=4.7K Ω. Cin, as Cout are chosen to filter the DC signal by the lowpass filters (R1,Cin) and (Rout, Cout). By taking R1=10K Ω, RL=150Ω, and Cin=2uF, Cout=220uF we provide a cutoff frequency below 10Hz. Use of the TSH7X in gain=-1 configuration: Some precautions have to be added, specially for low power supply application. A feedback capacitance Cf should be added for better stability. The table summarizes the impact of the capacitance Cf on the phase margin of the circuit. Parameter Value Vcc=+-2.5V Value Vcc=+-5V Unit Lum NL 0.1 0.3 % Lum NL Step 1 100 100 % Lum NL Step 2 100 99.9 % Lum NL Step 3 99.9 99.8 % Lum NL Step 4 99.9 99.9 % Lum NL Step 5 99.9 99.7 % Diff Gain pos 0 0 % Diff Gain neg -0.7 -0.6 % Diff Gain pp 0.7 0.6 % Diff Gain Step1 -0.5 -0.3 % Diff Gain Step2 -0.7 -0.6 % Diff Gain Step3 -0.3 -0.5 % Diff Gain Step4 -0.1 -0.3 % Diff Gain Step5 -0.4 -0.5 % Diff Phase pos 0 0.1 deg Diff Phase neg -0.2 -0.4 deg Diff Phase pp 0.2 0.5 deg Diff Phase Step1 -0.2 -0.4 deg Diff Phase Step2 -0.1 -0.4 deg Diff Phase Step3 -0.1 -0.3 deg Diff Phase Step4 0 0.1 deg Diff Phase Step5 -0.2 -0.1 deg IN R1 Vcc+ OUT R2 R3 C1 C3 C2 Cin Cout + - Cf R5 R4 RL IN R1 Vcc+ OUT R2 R3 C1 C3 C2 Cin Cout + - 1k Cf 1k RL |
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