LPC2377 datasheet(21/55 Pages) NXP

21 / 55 page

LPC2377_78_4

Product data sheet

Rev. 04 — 19 November 2008

21 of 55

NXP Semiconductors

LPC2377/78

Single-chip 16-bit/32-bit microcontroller

memory via the EMC, as well as the SRAM located on another AHB, if it is not being used

by the USB block. However, using memory other than the Ethernet SRAM, especially

off-chip memory, will slow Ethernet access to memory and increase the loading of its

AHB.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII

(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial

bus.

7.10.1 Features

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x full duplex ﬂow control and half duplex back pressure.

– Flexible transmit and receive frame options.

– Virtual Local Area Network (VLAN) frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory trafﬁc optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

– Receive ﬁltering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the

receive ﬁlters or a magic frame detection ﬁlter.

• Physical interface:

– Attachment of external PHY chip through standard RMII interface.

– PHY register access is available via the MIIM interface.

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