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CS4970X4 数据表(PDF) 21 Page - Cirrus Logic

部件名 CS4970X4
功能描述  32-bit High Definition Audio Decoder DSP Family
PDF  36 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS4970X4 数据表(HTML) 21 Page - Cirrus Logic

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Copyright 2008 Cirrus Logic
21
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
5.15 Switching Characteristics — UART
Figure 11. UART Timing
Parameter
Symbol
Min
Max
Unit
UART_CLK period1
1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.
tuclki
266
-
ns
UART_CLK duty cycle
-
40
60
%
Setup time for UART_RXD
tuckrxsu
5-
Hold time for UART_RXD
tuckrxdv
5-
ns
Delay from CLK transition to TXD transition
tucktxdv
-29
ns
ttxen
TBD
TBD
ns
ttxhz
TBD
TBD
ns
UART_CLK
UART_RXD
UART_TXD
t
uckrxsu
t
ucktxdv
t
uckrxdv
UART_TX_EN
t
txen
t
txhz



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