CS5522-ASZ datasheet(49/56 Pages) CIRRUS

49 / 56 page

CS5521/22/23/24/28

DS317F6

2.1 Clock Generator

XIN; XOUT - Crystal In; Crystal Out.

A gate inside the chip is connected to these pins and can be used with a crystal to provide the

master clock for the device. Alternatively, an external (CMOS compatible) clock can be

supplied into the XIN pin to provide the master clock for the device.

2.2 Control Pins and Serial Data I/O

CS - Chip Select.

When active low, the port will recognize SCLK. When high the SDO pin will output a high

impedance state. CS should be changed when SCLK = 0.

SDI - Serial Data Input.

SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.

SDO - Serial Data Output.

SDO is the serial data output. It will output a high impedance state if CS =1.

SCLK - Serial Clock Input.

A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins

respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin

will recognize clocks only when CS is low.

A0, A1 - Logic Outputs.

The logic states of A0-A1 mimic the states of the D22/D10-D23/D11 bits of the channel-setup

2.3 Measurement and Reference Inputs

AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- - Differential Analog Input.

Differential input pins into the CS5522 and CS5524 devices.

AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ - Single-Ended Analog Input.

Single-ended input pins into the CS5528.

VREF+, VREF- - Voltage Reference Input.

Fully differential inputs which establish the voltage reference for the on-chip modulator.

CS5522-ASZ 数据表(PDF) 49 Page - Cirrus Logic