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CS47048 数据表(PDF) 20 Page - Cirrus Logic

部件名 CS47048
功能描述  Audio SOC Processor Family
PDF  34 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS47048 数据表(HTML) 20 Page - Cirrus Logic

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CS47048 Data Sheet
Audio SOC Processor Family
20
Copyright 2008 Cirrus Logic
DS787A7
5.12 Digital Switching Characteristics — Serial Control Port - I2C Master Mode
Figure 7. Serial Control Port - I2C Master Mode Timing
Parameter
Symbol
Min
Max
Units
SCP_CLK frequency1
1.fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application.
fiicck
-400
kHz
SCP_CLK rise time
tiicr
-150
ns
SCP_CLK fall time
tiicf
-150
ns
SCP_CLK low time
tiicckl
1.25
-
µs
SCP_CLK high time
tiicckh
1.25
-
µs
SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition
tiicckcmd
1.25
µs
START condition to SCP_CLK falling
tiicstscl
1.25
-
µs
SCP_CLK falling to STOP condition
tiicstp
2.5
-
µs
Bus free time between STOP and START conditions
tiicbft
3-
µs
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
ns
Hold time SCP_SDA input after SCP_CLK falling
tiich
20
-
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
-18
ns
SCP_CLK
SCP_SDA
0
1
67
80
1
7
tiicckl
tiicckh
tiicsu
tiich
A6
A0
R/W
ACK
LSB
8
ACK
MSB
tiicstp
6
tiicdov
tiicbft
tiicstscl
tiicckcmd
fiicck
tiicckcmd
tiicf
tiicr
1/



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