AT89C5122DS-RDRUM datasheet(130/208 Pages) ATMEL

130 / 208 page

130

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Figure 75.

Data Frame Format (Mode 1)

Modes 2 and 3

Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 76)

consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one

programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin

and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON

tively, you can use the ninth bit as a command/data flag.

Figure 76.

Data Frame Format (Modes 2 and 3)

Transmission

(Modes 1, 2 and 3)

To initiate a transmission, write to SCON register, setting SM0 and SM1 bits according

to Figure 69 on page 128, and setting the ninth bit by writing to TB8 bit. Then, writing the

byte to be transmitted to SBUF register starts the transmission.

Reception

(Modes 1, 2 and 3)

To prepare for a reception, write to SCON register, setting SM0 and SM1 bits according

to Figure 69 on page 128, and setting REN bit. The actual reception is then initiated by a

detected high-to-low transition on the RXD pin.

Framing Error Detection

(Modes 1, 2 and 3)

Framing error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register as shown in

Figure 77.

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two devices. If a valid stop bit is not found, the software sets FE bit in

SCON register.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a chip reset clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on

stop bit instead of the last data bit as detailed in Figure 75 and Figure 76.

Figure 77.

Framing Error Block Diagram

Mode 1

Start bit

8-bit data

Stop bit

Modes 2 and 3

Start bit

9-bit data

Stop bit

SM0

SMOD0

PCON.6

SM0/FE

SCON.7

Framing Error

Controller

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