5

0273J–PEEPR–10/06

AT28BV256

5.6.1

Hardware Protection

Hardware features protect against inadvertent writes to the AT28BV256 in the following ways:

(a) V

out 10 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE high

or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on the

WE or CE inputs will not initiate a write cycle.

5.6.2

Software Data Protection

A software-controlled data protection feature has been implemented on the AT28BV256. Soft-

ware data protection (SDP) helps prevent inadvertent writes from corrupting the data in the

device. SDP can prevent inadvertent writes during power-up and power-down as well as any

other potential periods of system instability.

The AT28BV256 can only be written using the software data protection feature. A series of three

write commands to specific addresses with specific data must be presented to the device before

writing in the byte or page mode. The same three write commands must begin each write opera-

tion. All software write commands must obey the page mode write timing specifications. The

data in the 3-byte command sequence is not written to the device; the address in the command

sequence can be utilized just like any other location in the device.

Any attempt to write to the device without the 3-byte sequence will start the internal write timers.

No data will be written to the device; however, for the duration of t

tively be polling operations.

5.7

Device Identification

An extra 64 bytes of EEPROM memory are available to the user for device identification. By rais-

ing A9 to 12V

± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be

written to or read from in the same manner as the regular memory array.