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AT89C51CC02CA-RATUM 数据表(PDF) 70 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM 数据表(HTML) 70 Page - ATMEL Corporation |
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70 / 159 page ![]() 70 AT/T89C51CC02 4126L–CAN–01/08 Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 50. Machine Cycle Count To compute WD Timeout, the following formula is applied: Note: Svalue represents the decimal value of (S2 S1 S0) Find Hereafter computed Timeout values for f OSCXTAL = 12 MHz in X1 mode Table 51. Timeout Computation S2 S1 S0 Machine Cycle Count 00 0 2 14 - 1 00 1 2 15 - 1 01 0 216 - 1 01 1 2 17 - 1 10 0 2 18 - 1 10 1 219 - 1 11 0 220 - 1 11 1 2 21 - 1 S2 S1 S0 fOSC=12 MHz fOSC=16MHz fOSC=20 MHz 0 0 0 16.38 ms 12.28 ms 9.82 ms 0 0 1 32.77 ms 24.57 ms 19.66 ms 0 1 0 65.54 ms 49.14 ms 39.32 ms 0 1 1 131.07 ms 98.28 ms 78.64 ms 1 0 0 262.14 ms 196.56 ms 157.28 ms 1 0 1 524.29 ms 393.12 ms 314.56 ms 1 1 0 1.05 s 786.24 ms 629.12 ms 1 1 1 2.10 s 1.57 s 1.25 s FTime Out F osc 62 × WD X2 X2 ∧ 2 14 2 Svalue × () ----------------------------------------------------------------------------- = – |
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