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UPSD3233 数据表(PDF) 36 Page - STMicroelectronics |
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UPSD3233 数据表(HTML) 36 Page - STMicroelectronics |
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36 / 170 page  uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV 36/170 USART Interrupt – The USART Interrupt is generated by RI (receive interrupt) OR TI (transmit interrupt). – When the USART Interrupt is generated, the corresponding request flag must be cleared by software. The interrupt service routine will have to check the various USART registers to determine the source and clear the corresponding flag. – Both USART’s are identical, except for the additional interrupt controls in the Bit 4 of the additional interrupt control registers (A7H, B7H) Figure 16. Interrupt System Table 18. SFR Register SFR Addr Reg Name Bit Register Name Reset Value Comments 76 5 4 3 2 1 0 A7 IEA EDDC — — ES2 — — EI2C EUSB 00 Interrupt Enable (2nd) A8 IE EA — ET2 ES ET1 EX1 ET0 EX0 00 Interrupt Enable B7 IPA PDDC — — PS2 — — PI2C PUSB 00 Interrupt Priority (2nd) B8 IP — — PT2 PS PT1 PX1 PT0 PX0 00 Interrupt Priority AI06646 INT0 USART Timer 0 I2C INT1 DDC Timer 1 USB 2nd USART Timer 2 High Low Interrupt Sources IE / IP / IPA Priority Global Enable |
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