DAC7311 datasheet(28/41 Pages) TI

28 / 41 page

SERIAL INTERFACE

DACx311 Input Shift Register

DACx311 SYNC Interrupt

InvalidWriteSequence:

HIGHbefore16thFallingEdge

SYNC

ValidWriteSequence:

OutputUpdateson16thFallingEdge

CLK

SYNC

DB15

DB0

DB15

DB0

DAC5311

DAC6311

DAC7311

SBAS442 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com

the DACx311 compatible with high-speed DSPs. On

the 16th falling edge of the serial clock, the last data

The DACx311 has a 3-wire serial interface (SYNC,

bit is clocked in and the programmed function is

SCLK, and DIN) compatible with SPI, QSPI, and

executed.

Microwire interface standards, as well as most DSPs.

See the Serial Write Operation timing diagram for an

At this point, the SYNC line may be kept low or

example of a typical write sequence.

brought high. In either case, it must be brought high

for a minimum of 20ns before the next write

sequence so that a falling edge of SYNC can initiate

the next write sequence. As previously mentioned, it

The input shift register is 16 bits wide, as shown in

must be brought high again before the next write

Table 2. The first two bits (PD0 and PD1) are

sequence.

reserved control bits that set the desired mode of

operation

(normal

mode

any

one

three

power-down modes) as indicated in Table 5.

In a normal write sequence, the SYNC line is kept

The remaining data bits are either 12 (DAC7311), 10

low for at least 16 falling edges of SCLK and the DAC

(DAC6311), or 8 (DAC5311) data bits, followed by

is updated on the 16th falling edge. However,

don't care bits, as shown in Table 2, Table 3, and

bringing SYNC high before the 16th falling edge acts

Table 4, respectively.

as an interrupt to the write sequence. The shift

The write sequence begins by bringing the SYNC line

invalid. Neither an update of the DAC register

low. Data from the DIN line are clocked into the 16-bit

contents nor a change in the operating mode occurs,

shift register on each falling edge of SCLK. The serial

as shown in Figure 112.

clock frequency can be as high as 50MHz, making

Table 2. DAC5311 8-Bit Data Input Register

DB15

DB14

DB6

DB5

DB0

PD1

PD0

Table 3. DAC6311 10-Bit Data Input Register

DB15

DB14

DB4

DB3

DB0

PD1

PD0

Table 4. DAC7311 12-Bit Data Input Register

DB15

DB14

DB2

DB1

DB0

PD1

PD0

D11

D10

Figure 112. DACx311 SYNC Interrupt Facility

Submit Documentation Feedback

Product Folder Link(s): DAC5311 DAC6311 DAC7311

DAC7311 数据表(PDF) 28 Page - Texas Instruments

DAC7311 数据表(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载

链接网址

DAC7311 数据表(PDF) 28 Page - Texas Instruments

DAC7311 数据表(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表 下载

链接网址

数据表下载