ATA5423-PLSW datasheet(39/100 Pages) ATMEL

39 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

7.3.2

Control Register 2 (ADR 1)

Table 7-6.

Control Register 1 (Function of Bit 0)

T_MODE

Function

TX and RX function via TX/RX data buffer (default)

Transparent mode, TX/RX data buffer disabled, TX modulation data stream via pin

SDI_TMDI, RX modulation data stream via pin SDO_TMDO

Table 7-7.

Control Register 2 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2 and Bit 1)

FR6

FR5

FR4

FR3

FR2

FR1

FR0

Function

000

FREQ2 = 0

000

FREQ2 = 1

...

110

FREQ2 = 88 (default)

...

111

FREQ2 = 127

Note:

Tuning of f

RF LSBs (total 13 bits), frequency trimming resolution of fRF is fXTO/16384, which is

approximately 800 Hz (see section “XTO”, Table 4-1 on page 28)

Table 7-8.

Control Register 2 (Function of Bit 0 in RX Mode)

P_MODE

Function (RX Mode)

Pin IRQ is set to “1” if the bit check is successful (default)

No effect on pin IRQ if the bit check is successful

Table 7-9.

Control Register 2 (Function of Bit 0 in TX Mode)

P_MODE

Function (TX Mode)

Manchester modulator on (default)

Manchester modulator off (NRZ mode)

ATA5423-PLSW 数据表(PDF) 39 Page - ATMEL Corporation

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