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AT86RF212 数据表(PDF) 3 Page - ATMEL Corporation |
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AT86RF212 数据表(HTML) 3 Page - ATMEL Corporation |
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3 / 173 page ![]() 3 8168A-AVR-06/08 AT86RF212 Figure 1-1. AT86RF212 Block Diagram Voltage Regulator LNA Frequency Synthesis PPF BPF ADC AGC RX BBP TX Power TRX Buffer Configuration Registers SPI (Slave) TX BBP IRQ CLKM DIG1 /RST SLP_TR /SEL MISO MOSI SCLK RFN DIG2 FTN, BATMON XOSC Analog Domain Digital Domain Mixer Mixer LPF DAC PA RFP AES Control Logic DIG3/4 The receiver path is based on a low-IF architecture. After channel filtering and down- conversion the low-IF signal is sampled and applied to the digital signal processing part. Communication between transmitter and receiver is based on direct sequence spread spectrum with different modulation schemes and spreading codes. The AT86RF212 supports the IEEE 802.15.4-2006 standard mandatory BPSK modulation and optional O-QPSK modulation in the 800 and 900 MHz band. For applications not necessarily targeting IEEE compliant networks the radio transceiver supports proprietary High Data Rate Modes based on O-QPSK. A single 128 byte TRX buffer stores receive or transmit data. The AT86RF212 features hardware supported 128 bit security operation. The standalone AES encryption/decryption engine can be accessed in parallel to all PHY operational modes. Configuration of the AT86RF212, reading, and writing of data memory as well as the AES hardware engine are controlled by the SPI interface and additional control signals. On-chip low-dropout voltage regulators provide the analog and digital 1.8 V power supply. Control registers retain their settings in SLEEP mode when the regulators are turned off. The RX and TX signal processing paths are highly integrated and optimized for low power consumption. |
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