CMP0417AAx-E

CMOS LPRAM

Revision 0.5

Aug. 2006

8

Address

/CS

/UB, /LB

/WE

Data Out

tWC

tWR(4)

tBW

tWP(1)

High-Z

High-Z

Data Valid

tDW

tDH

Data in

tCW(2)

tAS(3)

tAW

1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with

asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write

ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to

the end of write.

2. tCW is measured from the /CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.

5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 160us.

Address

/CS

/UB, /LB

/WE

Data Out

tWC

tWR(4)

tBW

tWP(1)

High-Z

High-Z

Data Valid

tDW

tDH

Data in

tCW(2)

tAW

tAS(3)

Address

/CS

/UB, /LB

/WE

Data Out

tWC

tCW(2)

tWR(4)

tAW

tBW

tWP(1)

tAS(3)

High-Z

High-Z

Data Undefined

Data Valid

tDW

tDH

tOW

tWHZ

Data in