CMP0817BA2 datasheet(4/12 Pages) FIDELIX

4 / 12 page

CMP0817BAx-E

CMOS LPRAM

Revision 0.5

Aug. 2006

DC AND OPERATING CHARACTERISTICS

1. Capacitance is sampled, not 100% tested.

CAPACITANCE1) (f=1MHz , TA=25’C)

Max

Min

VIO=0V

CIO

Input/Output capacitance

VIN=0V

CIN

Input capacitance

Unit

Test Condition

Symbol

Item

/CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC

ISB1

Standby Current(CMOS)

Low Power Modes

/ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection

ISB0a

/ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection

ISB0b

/ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD)

ISB0

Deep Power Down

Current1)

-1

/CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC

ILO

Output leakage current

-1

VIN=VSS to VCC

ILI

Input leakage current

Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH,

VIN≤0.2V or VIN≥VCC-0.2V

ICC1

Average operating current

0.2VCCQ

IOL=0.5mA

VOL

Output low voltage

Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH,

VIN=VIL or VIH

ICC2

0.8VCCQ

IOH=-0.5mA

VOH

Output high voltage

0.3

Max

Typ

Min

/ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection

ISB0c

/CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL

ISB

Standby Current(TTL)

Unit

Test Conditions

Symbol

Item

1. CMP0817BA2 & CMP0817BA5 products support DPD(Deep Power Down) Current

CMP0817BA2 数据表(PDF) 4 Page - FIDELIX

CMP0817BA2 数据表(HTML) 4 Page - FIDELIX

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

数据表下载