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6399A–DRMSD–13-Oct-08

ATSAM2553

9.

Recommended Crystal Compensation

Figure 9-1.

Recommend Crystal Compensation

10. Recommended Board Layout

Like all HCMOS high integration ICs, following simple rules of board layout is mandatory for reli-

able operations:

• GND, VD33, VD18 distribution, decouplings

All GND, AGND, VD33, VD18, VA33 pins should be connected. A GND plane is strongly recom-

mended below the ATSAM2553. The board GND + VD33 planes could be in grid form to

minimize EMI.

Recommended VD18 decoupling is 0.1µF, close to the VD18 pin and 470pF in parallel with 2.2

or 4.7µF, close to OUTVC18 pin. VD33 requires 0.1 µF at each corner of the IC with an addi-

tional 10 µFT capacitor that should be placed close to the crystal.

• Crystal

The paths between the crystal, the crystal compensation capacitors and the ATSAM2553 should

be short and shielded. The ground return from the compensation capacitors should be the GND

plane from ATSAM2553.

• Busses

Parallel layout from DB0-DB7 and WA0-WA24/WD0-WD15 should be avoided. The DB0-DB7

bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0-

WA24/WD0-WD15 which can corrupt address and/or data on these busses.

A ground plane should be implemented below the DB0-DB7 bus.

A ground plane should be implemented below the WA0-WA24/WD0-WD15 bus, which connects

both to the ROM/Flash grounds and to the ATSAM2553.

• Analog section

A specific AGND ground plane should be provided, which connects by a single trace to the GND

ground. No digital signals should cross the AGND plane. Refer to the CODEC vendor recom-

mended layout for correct implementation of the analog section