On-line Phase Timing (Acquisition and Elaboration) Working Frequency 40MHz

OFL

I0-I6

DATA0

DATAn

DATA1

MCLK

FIN

NP

EP

FIN de tection

DATA0 acq uisition

DATA1 a cquisition

DATAn acquisition

Timing Table Description: ON-LINE phase

- MCLK [INPUT] must be connectedwith the external synchronization signal.

- OFL [INPUT] must be set low to enable the acquisition/elaboration phase of W.A.R.P..

- FIN [INPUT] must be set high for at least 1clock period to start the acquisition phase. OFL must already

be low since at least 4 clock periods before providing a FIN pulse. FIN duration must be in the range

[1clock,2clock periods]. FIN pulse mustn’t coincide with NP transitions.

- NP [OUTPUT] will remain low during the acquisition phase.

- The input data must be sent to I0-I6 after OFL has been set low and FIN has been set high. Data situated

in I0-I6 are stored into its internal registers at each next rising edge of the MCLK.

- After the current inputs have been acquired, the NP [OUTPUT] high signal informs that the elaboration

phase can start. This information is provided thanks to the configuration stored in the program memory.

Figure 10. Input/Output Connection Block Diagram

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W.A.R.P.1.1