HV300/HV310

4

Pinout

Pin Description

PWRGD – The Power Good Output Pin is held inactive on initial

power application and will go active when the external MOSFET

is fully turned on. This pin may be used as an enable control

when connected directly to a PWM power module.

OV – This Over Voltage sense pin, when raised above its high

threshold will immediately cause the GATE pin to be pulled low.

The GATE pin will remain low until the voltage on this pin falls

below the low threshold limit, initiating a new start-up cycle.

UV – This Under Voltage sense pin, when below its low threshold

limit will ensure that the GATE pin is low. The GATE pin will

remain low until the voltage on this pin rises above the high

threshold, initializing a new start-up cycle.

circuit.

V

circuit.

RAMP – This pin provides a current output so that a timing

ramp voltage is generated when a capacitor is connected. The

initial portion of the ramp provides a time delay, which in

conjunction with the Under Voltage detection circuit eliminates

circuit card insertion contact bounce. The RAMP pin also controls

the delay between the current limit mode disengaging and the

PWRGD signal activating; as well as the current rise profile

after the initial turn on delay.

GATE – This is the Gate Driver Output for the external N-

Channel MOSFET.

SENSE – The current sense resistor connected from this pin to

V

mode is established when the voltage drop across this resistor

reaches 50mV.

Functional Block Diagram

1

2

3

4

8

7

6

5

PWRGD

OV

RAMP

UV

GATE

SENSE

PWRGD Logic

Model

Condition

PWRGD

HV300

NOT READY

0

V

EE

READY

1

HI Z

HV310

NOT READY

1

HI Z

READY

0

Buffer

LOGIC

UV

OV

SENSE

GATE

RAMP

Vref

UVLO

and

POR

Band Gap

Reference

Internal

Supply

Regulator

VINT

Vref

HV300:PWRG

HV310: PWRGD

+

–

10µA

Trans-

conductor

5kΩ