4

HV57708

HV

3

7

11

•

•

•

HV

63

HV

4

8

12

•

•

•

HV

64

HV

2

6

10

•

•

•

HV

62

HV

1

5

9

•

•

•

HV

61

POL

PP

V

OUT

BL

D 4

OUT

OUT

OUT

OUT

OUT

OUT

OUT

LE

I

D 4

O

SR4

SR3

SR2

SR1

CLK

DIR

GND

DD

V

D 3

O

D 2

O

D 1

O

D 3

I

D 2

I

D 1

I

D 1

O

D 2

O

D 3

O

D 4

O

D 1

I

D 2

I

D 3

I

D 4

I

Functional Block Diagram

Inputs

Outputs

Function

Shift Reg

HV Outputs

Data Out

All O/P High

X

X

X

L

L

X

H

All O/P Low

X

X

X

L

H

X

L

O/P Normal

X

X

X

H

H

X

No inversion

O/P Inverted

X

X

X

H

L

X

Inversion

L

HHH

X

L

L

H

HHH

X

H

H

LH

H

L

X

L

H

HH

H

L

X

H

L

Data Stored/

XX

LH

HX

*

Stored Data

Latches Loaded

XX

LH

LX

*

Inversion of

Stored Data

H

H

H

H

New H or L

L

H

H

H

Previous

H or L

L

H

H

L

Previous

H or L

H

H

H

L

New H or L

Data

CLK

LE

BL

POL

DIR

Note:

Function Table

I/O Relation

Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc.

↑

Data Falls

Through

(Latches

Transparent)

↑

↑

↑

↑

↑

↑

↑