3-30

TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

Figure 8. Typical Dual Slope A/D Converter System Timing

,,





,,

AUTO -ZERO

INTEGRATE

FULL SCALE INPUT

REFERENCE

DEINTEGRATE

OVERSHOOT

INTEGRATOR

OUTPUT

ZERO

CONVERTER

STATUS

TIME

INTEGRATOR

VOLTAGE

COMPARATOR

OUTPUT

AB INPUTS

CONTROLLER

OPERATION

NOTES

COMPARATOR DELAY

BEGIN CONVERSION

WITH AUTO-ZERO PHASE

(POSITIVE INPUT SHOWN)

SAMPLE INPUT POLARITY

The length of this phase

is chosen almost arbitrarily

but needs to be long enough

to null out worst case errors

(see text)

MINIMIZING OVERSHOOT

WILL MINIMIZE I.O.Z. TIME

READY FOR NEXT

CONVERSION

(AUTO-ZERO IS IDLE

STATE)

TIME INPUT

INTEGRATION

PHASE

CAPTURE

DEINTEGRATION

TIME

INTEGRATOR

OUTPUT

ZERO PHASE

COMPLETE

UNDEFINED

A = 0

B = 1

A = 1

0 FOR NEGATIVE INPUT

1 FOR POSITIVE INPUT

B = 0

B = 1

B = 0

A = 1

A = 0

VINT

TYPICALLY = tINT

tINT

0

A

B

COMPARATOR DELAY +

PROCESSOR LATENCY

is that, during the initial stage of input integration when the

integrator voltage is low, the comparator may be affected by

noise and its output unreliable. Once integration is well

underway, the comparator will be in a defined state.

Reference Deintegration

The length of this phase must be precisely measured

from the transition of AB from 10 to 11 to the falling edge of

CMPTR. The comparator delay contributes some error in

timing this phase. The typical delay is specified to be 2

µsec.

This should be considered in the context of the length of a

single count when determining overall system performance

and possible single-count errors. Additionally, Overshoot

will result in charge accumulating on the integrator after its

output crosses zero. This charge must be nulled during the

Integrator Output Zero phase.

Integrator Output Zero phase

The comparator delay and the controller's response

latency may result in Overshoot causing charge buildup on

the integrator at the end of a conversion. This charge must

be removed or performance will degrade. The Integrator

Output Zero phase should be activated (AB = 00) until

CMPTR goes high. It is absolutely critical that this phase be

terminated immediately so that Overshoot is not allowed to

occur in the opposite direction. At this point, it can be

assured that the integrator is near zero. Auto Zero should be

entered (AB = 01) and the TC5xx held in this state until the

next cycle is begun.