TC7106CPL datasheet(13/19 Pages) TELCOM

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TELCOM SEMICONDUCTOR, INC.

Analog Common (Pin 32)

The analog common pin is set at a voltage potential

approximately 3.0V below V+. The potential is guaranteed

to be between 2.7V and 3.35 V below V+. Analog common

is tied internally to the N channel FET capable of sinking

20mA. This FET will hold the common line at 3.0V should an

external load attempt to pull the common line toward V+.

Analog common source current is limited to 10

µA. Analog

common is therefore easily pulled to a more negative

voltage (i.e., below V+ – 3.0V).

The TC7106A connects the internal V+IN and V

–

IN inputs

to analog common during the auto-zero cycle. During the

reference-integrate phase, V–

IN is connected to analog com-

mon. If V–

IN is not externally connected to analog common,

a common-mode voltage exists. This is rejected by the

converter's 86dB common-mode rejection ratio. In battery

operation, analog common and V–

IN are usually connected,

removing common-mode voltage concerns. In systems where

V–

IN is connected to the power supply ground or to a given

voltage, analog common should be connected to V–

IN.

The analog common pin serves to set the analog section

reference or common point. The TC7106A is specifically

designed to operate from a battery or in any measurement

system where input signals are not referenced (float) with

respect to the TC7106A power source. The analog common

potential of V+ – 3.0V gives a 6 V end of battery life voltage.

The common potential has a 0.001%/% voltage coefficient

and a 15

Ω output impedance.

With sufficiently high total supply voltage (V+ – V–

> 7.0V) analog common is a very stable potential with

excellent temperature stability—typically 20ppm/

°C. This

potential can be used to generate the reference voltage. An

external voltage reference will be unnecessary in most

cases because of the 50ppm/

°C maximum temperature

coefficient. See Internal Voltage Reference discussion.

Test (Pin 37)

The TEST pin potential is 5V less than V+. TEST may be

used as the negative power supply connection for external

CMOS logic. The TEST pin is tied to the internally generated

negative logic supply (Internal Logic Ground) through a

500

Ω resistor in the TC7106A. The TEST pin load should be

no more than 1mA .

If TEST is pulled to V+ all segments plus the minus sign

will be activated. Do not operate in this mode for more than

several minutes with the TC7106A. With TEST = V+ the LCD

segments are impressed with a DC voltage which will

destroy the LCD.

The TEST pin will sink about 10mA when pulled to V+.

Internal Voltage Reference Stability

The analog common voltage temperature stability has

been significantly improved (Figure 10). The “A” version of

the industry standard circuits allow users to upgrade old

systems and design new systems without external voltage

references. External R and C values do not need to be

changed. Figure 11 shows analog common supplying the

necessary voltage reference for the TC7106A/TC7107A.

Figure 10. Analog Common Temperature Coefficient

Figure 11. Internal Voltage Reference Connection

TYPICAL

MAXIMUM

SPECIFIED

TYPICAL

NO MAXIMUM

SPECIFIED

200

180

160

140

120

100

ICL7136

NO MAXIMUM

SPECIFIED

7106A

ICL7106

MAXIMUM

LIMIT

–

ANALOG

COMMON

TC7106A

TC7107A

VREF

24k

Ω

VREF

–

VREF

SET VREF = 1/2 VFULL SCALE

TC7106

TC7106A

TC7107

TC7107A

3-1/2 DIGIT A/D CONVERTERS

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