LT6553

9

6553f

TYPICAL APPLICATIO

RGB Buffer Demo Board

The DC714 Demo Board illustrates optimal routing,

bypassing and termination using the LT6553 as an

RGB video buffer. The schematic is shown in Figure 1. All

inputs and outputs are routed to have a characteristic

impedance of 75

Ω and 75Ω input shunt and output series

terminations are connected as close to the part as pos-

sible. For ideal operation, a 75

Ω load termination should

be connected at the output. The LT6553’s gain of 2 will

compensate for the resulting divider between the series

and load termination resistors.

Figure 1. DC714 Demo Board Schematic

J4

BANANA JACK

10

11

12

13

14

15

16

R6

75

Ω

R5

75

Ω

R4

75

Ω

R1

75

Ω

R2

75

Ω

R3

75

Ω

Z = 75

Z = 75

Z = 75

Z = 75

C1

4700pF

9

INB

AGND

ING

AGND

INR

DGND

EN

8

7

6

5

4

3

2

1

OUTB

OUTG

OUTR

LT6553

6553 F01

C2

470pF

C3

4700pF

C4

10

µF, 16V

1210

J2

BANANA

JACK

J9

5

1

OUTR

4

3

2

C5

470pF

DUAL

SINGLE

C6

1000pF

C7

470pF

C8

4700pF

C9

10

µF, 16V

1210

J10

5

J12

BNC

NOTE 5

BNC x3

5

1

CAL

4

3

2

1

OUTG

4

3

2

J11

5

1

OUTB

4

3

2

J8

BNC

5

1

J3

BANANA

JACK

E3

AGND

E1

EN

E2

DGND

CAL

AGND

4

3

2

13

2

JP3

SUPPLY

ENABLE

EXT

3

1 2

JP1

CONTROL

J5

5

1

INR

4

3

2

J6

5

BNC

× 3

1

ING

4

3

2

J7

5

1

Z = 75

Z = 75

Z = 75

INB

4

3

2

AGND

FLOAT

3

1 2

JP2

DGND

J1

50

Ω BNC

EN

5432

1

APPLICATIO S I FOR ATIO

If the AGND pins are not connected directly to a low

impedance ground plane, they must be carefully bypassed

to maintain minimal impedance over frequency. Pin 6 is a

shared connection of the gain resistors of both channel G

and channel B, and any resistance external to this node can

significantly decrease the isolation between those chan-

nels. Although crosstalk will be very dependent on the

board layout, a recommended starting point for bypass

capacitors would be 470pF as close as possible to each

AGND pin with one 4700pF capacitor in parallel.

To maintain the LT6553’s channel isolation, it is beneficial

to shield parallel input and output traces using a ground

plane or power supply traces. Vias between topside and

backside metal may be required to maintain a low

inductance ground near the part where numerous traces

converge.

ESD Protection

The LT6553 has reverse-biased ESD protection diodes on

all pins. If any pins are forced a diode drop above the

positive supply or a diode drop below the negative supply,

large currents may flow through these diodes. If the

current is kept below 10mA, no damage to the devices will

occur.