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MC-ACT-VME32-NET 数据表(PDF) 3 Page - Actel Corporation

部件名 MC-ACT-VME32-NET
功能描述  Flexible slave VME controller Full interrupt controller (ROAK)
PDF  5 Pages
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制造商  ACTEL [Actel Corporation]
网页  http://www.actel.com
标志 ACTEL - Actel Corporation

MC-ACT-VME32-NET 数据表(HTML) 3 Page - Actel Corporation

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Between the user part and the VME controller, the transfer of interrupt information is based on the request/acknowledge protocol.
When an interrupt occurs on the user part, it generates an interrupt request on the VME controller through the signal USER_IREQ. Depending on the value defined
by the user part on the vector USER_ILEV, the VME controller activates an interrupt on the respective interrupt line VME_IRQ_N(x) (USER_ILEV = 1 -> VME_IRQ_
N(1), USER_ILEV = 7 -> VME_IRQ_N(7)). Interrupt level 7 has the highest priority and interrupt level 1 has the lowest.
Since there, the interrupt handler acknowledges the interrupt by asserting a low state on the signal VME_IACK_N. This signal will be transmitted to all modules and
as well in the first module of the daisy-chain. The modules which didn’t generate an interrupt just assert the VME_IACKIN_N signal to the VME_IACKOUT_N. A
module which generated an interrupt will detect the acknowledge at the falling edge and compare the VME_ADDR(3:1) with the interrupt level register (USER_ILEV)
to determine if it has the priority (depending on the level) to execute the interrupt or not. In case of not, it will assign the VME_IACKIN_N to VME_IACKOUT_N. In the
other case (the corresponding module has the priority), the high state is asserted to the VME_IACKOUT_N signal in order to break the daisy-chain and avoid other
modules taking the interrupt acknowledge. During the acknowledge, the module transfers the interrupt vector register defined by the user (USER_IVEC) on the VME
data bus (VME_DATA_OUT). When the data are valid, the VME controller drives the VME_DTACK_N signal low, allowing the master and interrupt handler executing
next commands.
On the user part, the interrupt is acknowledged with the signal USER_IACK which clears the pending interrupt request.
Device Requirements
Family
Device
Utilization
Performance
COMB
SEQ
Total
SX-A
A54SX72A-STD
220 (6%)
196 (10%)
416 (7%)
62 MHz
ProASIC3
A3PE600-STD
n/a
n/a
536 (4%)
82 MHz
ProASICPLUS
APA600-STD
n/a
n/a
672 (3%)
58 MHz
Axcelerator
AX500-STD
216 (4%)
196 (8%)
412 (5%)
86 MHz
Table 1: Device Utilization and Performance
Verification and Compliance
Complete functional and timing simulation has been performed on the VME using ModelSim 5.5e. This core has also been used successfully in customer designs.
Signal Descriptions
The following signal descriptions define the IO signals.
Signal
Direction
Description
CLK
Input
Clock: System clock. This clock is provided on the board and doesn’t coming from the VME bus
RESET_N
Input
System reset: Asynchronous system reset, active low.
VME_ADDR[31:1]
Input
VME Address Bus: The smallest addressable unit is the byte location. Masters use address lines to select
the data which has to be accessed.
VME_AM[5:0]
Input
VME Address Modifier Bus: Allow the master to pass additional binary information to the slave during data
transfer cycles.
VME_DATA_IN[31:0]
Input
VME Data Bus In: 32 write data lines are available. Depending on the control signals, only one or two byte(s)
can be used for the transfer on the user part.
VME_DATA_OUT[31:0]
Output
VME Data Bus Out: 32 read data lines. For each access, the 32 data bits are read.
VME_EXT_DRV_N
Output
VME External Data Drive: Active low drive enable signal for external bidirectional data bus drivers.
VME_INT_DRV_N
Output
VME Internal Data Drive: Active low drive enable signal for internal bidirectional data bus drivers.
VME_EXT_DDIR
Output
VME External Data Direction: Direction control signal for internal bidirectional data bus drivers. High
indicates data to VME bus and low from VME bus.
VME_LWORD_N
Input
VME Long Word: Active low signal indicating long word access.
VME_DTACK_N
Output
VME Data Acknowledge: This active low signal acknowledges the data transfer. It has to be connected to an
open collector driver.
VME_AS_N
Input
VME Address Strobe: clocks with falling edge the internal synchronization signals like VME_ADDR and
VME_AM. It is also used as data signal for access start detection.
VME_DS0_N
Input
VME Data Strobe 0: Active low signal used for the selected location part of the data.



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