Fast UART

Memec Design

February 25, 2003

2

Optimized for

Core Deliverables

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Netlist Version

o

Netlist compatible with the Actel Designer place and route tool

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RTL Version

o

VHDL Source Code

o

Test Bench

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All

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User Guide

Synthesis and Simulation Support

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Synthesis: Synplicity

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Simulation: ModelSim

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Other tools supported upon request

Verification

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Test Bench

Figure 1:Block Diagram

UART-F

clk

reset_n

fuart_config.data_78

fuart_config.par_ebl

fuart_config.par_pol

fuart_config.stop_12

fuart_config.tx_run

fuart_config.rx_run

fuart_config.baudrate

fuart_tx_pin

fuart_rx_pin

fuart_tx_busy

fuart_tx_data

fuart_tx_we

fuart_rx_data

fuart_rx_ready

fuart_par_error

fuart_form_error

TX Unit

RX Unit

Configuration