Reed-Solomon Encoder

Memec Design

April 24, 2003

4

Optimized for

Reed-Solomon Encoder Variations

Various forms of the core have been developed. One supports high data rates where area is a secondary concern.

Another supports low data rates where a high-speed system clock is available and area is a primary concern. The

cores work for any valid codeword length and can be customized to support either fixed or variable values of parity

symbols. The core has been developed in two different approaches. One approach is optimized for encoders with a

single value of t. The other approach is optimized for encoders with selectable values of t.

The RSENC-INTELSAT is a precustomized core that calculates a selectable 14, 16, 18, or 20 parity symbols (t = 7,

8, 9, or 10) and is compliant with the IESS-308 Intelsat standard. The primitive polynomial and generator polynomial

implemented is P(x)= x

input control signal selects between four different codeword/message lengths: RS(126,112), RS(194,178),

RS(219,201), and RS(225,205). The RSENC-INTELSAT core is delivered as Verilog RTL source code. Detailed

timing and pin descriptions of the RSENC-INTELSAT can be found in the User’s Guide available from MemecCore.

The RSENC-DVB is a precustomized core that calculates 16 parity symbols and is compliant with the DVB

standard. The primitive polynomial and generator polynomial implemented is P(x)=x

α

n-k=16. Thus, the largest code supported by this core is R(255,239). The DVB standards specify a code of

RS(204,188).

Parameter

Symbol

DVB

Intelsat

Primitive Polynomial

P(x)

x

x

Generator Polynomial

G(x)

(x-

α

(x-

α

Bits per symbol

m

8

8

Codeword Length

n

204 (Note 1)

126, 194, 219, 225

Message Word Length

k

188

112, 178, 201, 205 (Note 2)

Parity Symbols (n-k)

2t

16

14, 16, 18, 20

Table 1: Reed-Solomon Encoder Parameters

Notes:

1. Core is adaptable to any RS(n,k) where n-k=16 and largest code being RS(255,239).

2. Selected by 2-bit input control signal for RS(126,112), RS(194,178), RS(219,201), and RS(225,205).

Device Requirements

Family

Device

Utilization

Performance

COMB

SEQ

Total

Axcelerator

AX500-3

6%

10%

7%

119 MHz

ProASIC

PLUS

APA075

n/a

n/a

34%

51 MHz

Table 2: Device Utilization and Performance*

*Note: The data provided is for an encoder with RS(255,225), G(x)=120, P(x)=125, m=8.

Verification and Compliance

Functional and timing simulation has been performed on the RSENC using Verilog Test Benches. Simulation

vectors used for verification are provided with the core. This core has also been used successfully in customer

designs.