Device Requirements

Family

Device

Utilization

Performance

COMB

SEQ

Tiles

Axcelerator

AX250

38%

73%

n/a

131 MHz

ProASIC3

A3PE600

n/a

n/a

20%

81 MHz

APA150

n/a

n/a

52%

80 MHz

Table 1: Device Utilization and Performance

Verification and Compliance

The testbench is self-checking, which means that if there is an error detected in the start word, end word, or payload the testbench will assert one or both of two error

signals. The test checks for errors at two stages in the testbench: when the cells are looped back through the Slave device (SIG_LOOP_ERROR_OUT) and upon

reading out of the Master device (SIG_ERROR_OUT).

Signal Descriptions

The following signal descriptions define the IO signals.

Signal

Width

Direction

Description

RD_DATA

8/16

Output

Read data bus for the FIFO

RD_ENB

1

Input

Read enable signal for the FIFO

RD_CLK

1

Input

Read clock for the FIFO

RD_FLAG

1

Output

FIFO packet available signal

RESET_N

1

Input

Reset signal from user logic

WR_DATA

8/16

Input

Write data bus for FIFO

WR_FLAG

1

Output

Write flag indicating if FIFO can accept another cell

WR_ENB

1

Input

Write enable signal for FIFO

WR_CLK

1

Input

System clock for all registers in this block

TXCLK

1

Input

100 MHz utopia clock

TXDATA

8/16/32

Input

Utopia data bus, 8, 16 or 32-bit selectable

TXENB_N

1

Input

Utopia enable signal used for throttle control

TXCLAV

1 < N < 4

Output

Utopia cell buffer available signal(s) used to indicate that the slave has room for a cell

TXSOC

1

Input

Utopia start of cell signal used to flag the first byte/word in the cell

TXPRTY

1

Input

Utopia parity signal used for odd parity on TXDATA

TXADDR

8

Input

Utopia address bus used for polling

RXCLK

1

Input

100 MHz utopia clock

RXDATA

8/16/32

Output

Utopia data bus, 8, 16 or 32-bit selectable

RXENB_N

1

Input

Utopia enable signal used for throttle control

RXCLAV

1 < N < 4

Output

Utopia cell buffer available signal(s) used to indicate that the slave has room for a cell

RXPRTY

1

Output

Utopia parity signal used for odd parity on TXDATA

RXSOC

1

Output

Utopia start of cell signal used to flag the first byte/word in the cell

RXADDR

8

Input

Utopia address bus used for polling

Table 2: Core I/O Signals