© 2003 by Eureka Technology Inc.

4962 El Camino Real,

Los Altos, CA 94022, USA

Tel: 1 650 960 3800

Fax: 1 650 960 3805

http://www.eurekatech.com

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Eureka Technology

• Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740,

750 and 8260.

• Supports up to eight PowerPC bus masters with unlimited slave device support.

• Supports two outstanding bus accesses.

• Supports address only transfer and address bus retry.

• Independent address bus and data bus tenure with separate bus grant and data

bus grant.

•Option for fixed priority assignment or rotating priority scheme.

• Designed for ASIC or programmable logic device implementations in various

system environments.

• Fully static design with edge triggered flip-flops.

• Optimized for Actel SX-A, RTSX-S, AX, and APA product families.

The EP300 PowerPC bus arbiter provides all the necessary functions to arbitrate

multiple bus masters directly connected to the PowerPC host bus. The arbiter sup-

ports separate address and data bus tenure to realize the high performance allowed

by the PowerPC bus architecture. Separate address bus grant and data bus grant

signals are provided for each master device on the bus. The arbiter uses sophisti-

cated built-in state machines to coordinate the address bus tenure and the data bus

tenure. At any given cycle, up to two simultaneous bus accesses are allowed.

FEATURES

DESCRIPTIONS

EP300 PowerPC Bus Arbiter

Product Summary

Previous

master

data bus

grant

Address bus

Priority

Data bus grant

One to each device

Bus request

One from each device

TS# ABB# DBB# TT

PowerPC Bus

Bus grant

One to each device