LTC1098ACN8-PBF datasheet(21/32 Pages) LINER

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LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

APPLICATIONS INFORMATION

Figure 7. LTC1098(L) “+” and “–” Input Settling Windows

(Figure 6) and connect the center point to the MPU input.

It should be noted that to get full shutdown, the CS input

of the LTC1096/LTC1098 must be driven to the VCC volt-

age. This would require adding a level shift circuit to the

CS signal in Figure 6.

Figure 6. Interfacing a 9V Powered LTC1096 to a 5V System

BOARD LAYOUT CONSIDERATIONS

Grounding and Bypassing

The LTC1096(L)/LTC1098(L) should be used with an analog

ground plane and single point grounding techniques. The

GND pin should be tied directly to the ground plane.

The VCC pin should be bypassed to the ground plane with

a 1μF tantalum with leads as short as possible. If power

supply is clean, the LTC1096(L)/LTC1098(L) can also oper-

ate with smaller 0.1μF surface mount or ceramic bypass

capacitors. All analog inputs should be referenced directly

to the single point ground. Digital inputs and outputs should

be shielded from and/or routed away from the reference

and analog circuitry.

SAMPLE-AND-HOLD

Both the LTC1096(L) and the LTC1098(L) provide a built-in

sample-and-hold (S&H) function to acquire signals. The

S&H of the LTC1096(L) acquires input signals from “+”

input relative to “–” input during the tWAKEUP time (see

Figure 1). However, the S&H of the LTC1098(L) can sample

input signals in the single-ended mode or in the differential

inputs during the tSMPL time (see Figure 7).

Single-Ended Inputs

The sample-and-hold of the LTC1098(L) allows conversion

of rapidly varying signals. The input voltage is sampled

during the tSMPL time as shown in Figure 7. The sampling

interval begins as the bit preceding the MSBF bit is shifted

+IN

–IN

GND

VCC

CLK

DOUT

VREF

50k

4.7μF

MPU

(e.g. 8051)

P1.4

P1.3

P1.2

10968 F06

DIFFERENTIAL INPUTS

COMMON MODE RANGE

0V TO 6V

LTC1096

OPTIONAL

LEVEL SHIFT

CLK

DIN

DOUT

"+" INPUT

"–" INPUT

SAMPLE

HOLD

"+" INPUT MUST

SETTLE DURING

THIS TIME

tSMPL

tCONV

SGL/DIFF

START

MSBF

DON'T CARE

1ST BIT TEST "–" INPUT MUST

SETTLE DURING THIS TIME

10968 F07

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