LTC1096/LTC1096L

LTC1098/LTC1098L

16

10968fc

The wake-up time is inherently provided for the LTC1098(L)

with setup time = 1μs (see Figure 2).

Data Transfer

The CLK synchronizes the data transfer with each bit being

transmitted on the falling CLK edge and captured on the

rising CLK edge in both transmitting and receiving sys-

tems. The LTC1098(L) first receives input data and then

transmits back the A/D conversion result (half duplex).

be tied together allowing transmission over just three

Data transfer is initiated by a falling chip select (CS) signal.

After CS falls the LTC1098(L) looks for a start bit. After the

start bit is received, the 3-bit input word is shifted into the

conversion. After one null bit, the result of the conversion

Figure 1. LTC1096(L) Operating Sequence

CS should be brought high. This resets the LTC1098(L) in

preparation for the next data exchange.

The LTC1096(L) does not require a configuration input

feras shown in the LTC1096(L) operating sequence. After

Bringing CS high resets the LTC1096(L) for the next data

exchange.

CLK

CS

B7*

B6

B5

B4

B3

B2

B1

B0

B1

B2

B3

B4

B5

B6

B7

NULL

BIT

Hi-Z

10968 F01

POWER

DOWN

Hi-Z

CLK

CS

POWER

DOWN

B0

B1

B2

B3

B4

B5

B6

B7

Hi-Z

HI-Z

NULL

BIT

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.

(MSB)

(MSB)

APPLICATIONS INFORMATION

CS

SHIFT MUX

ADDRESS IN

1 NULL BIT

SHIFT A/D CONVERSION

RESULT OUT

10968 AI01