LTC4267IGN-1-PBF datasheet(13/32 Pages) LINER

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LTC4267-1

42671f

Figure 5. LTC4267-1 VPORTN Undervoltage Lockout

the classiﬁcation current is reenabled. C1 will discharge

through the PD circuitry and the POUT pin will go to a high

impedance state.

limit because the load capacitor is charged with a current

below the IEEE inrush current limit speciﬁcation.

As the LTC4267-1 switches from the low to high level

current limit, the current will increase momentarily. This

current spike is a result of the LTC4267-1 charging the

last 1.5V at the high level current limit. When charging a

10μF capacitor, the current spike is typically 100μs wide

and 125% of the nominal low level current limit.

The LTC4267-1 stays in the high level current limit mode

until the input voltage drops below the UVLO turn-off

threshold. This dual level current limit provides the sys-

tem designer with the ﬂexibility to design PDs which are

compatible with legacy PSEs while also being able to take

advantage of the higher power allocation available in an

IEEE 802.3af system.

During the current limited turn on, a large amount of

power is dissipated in the power MOSFET. The LTC4267-1

PD interface is designed to accept this thermal load and

is thermally protected to avoid damage to the onboard

power MOSFET. Note that in order to adhere to the IEEE

802.3af standard, it is necessary for the PD designer to

ensure the PD steady state power consumption falls within

the limits shown in Table 2. In addition, the steady state

current must be less than ILIM_HI.

Power Good

The LTC4267-1 PD Interface includes a power good circuit

(Figure 6) that is used to indicate that load capacitor C1

is fully charged and that the switching regulator can start

operation. The power good circuit monitors the voltage

across the internal UVLO power MOSFET and

⎯P⎯W⎯R⎯G⎯D is

asserted when the voltage falls below 1.5V. The power

good circuit includes hysteresis to allow the LTC4267-1 to

operate near the current limit point without inadvertently

disabling

⎯P⎯W⎯R⎯G⎯D. The MOSFET voltage must increase to

3V before

⎯P⎯W⎯R⎯G⎯D is disabled.

If a sudden increase in voltage appears on the input line,

this voltage step will be transferred through capacitor C1

and appear across the power MOSFET. The response of the

LTC4267-1 will depend on the magnitude of the voltage

step, the rise time of the step, the value of capacitor C1

and the switching regulator load. For fast rising inputs,

APPLICATIO S I FOR ATIO

Input Current Limit

IEEE 802.3af speciﬁes a maximum inrush current and

also speciﬁes a minimum load capacitor between the

VPORTP and POUT pins. To control turn-on surge current

in the system, the LTC4267-1 integrates a dual level cur-

rent limit circuit with an onboard power MOSFET and

sense resistor to provide a complete inrush control circuit

without additional external components. At turn-on, the

LTC4267-1 will limit the input current to the low level,

allowing the load capacitor to ramp up to the line voltage

in a controlled manner.

The LTC4267-1 has been speciﬁcally designed to interface

with legacy PSEs which do not meet the inrush current

requirement of the IEEE 802.3af speciﬁcation. At turn-on

the LTC4267-1 current limit is set to the lower level. After

C1 is charged up and the POUT– VPORTNvoltage difference

is below the power good threshold, the LTC4267-1 switches

to the high level current limit. The dual level current limit

allows legacy PSEs with limited current sourcing capability

to power up the PD while also allowing the PD to draw full

power from an IEEE 802.3af PSE. The dual level current

limit also allows use of arbitrarily large load capacitors.

The IEEE 802.3af speciﬁcation mandates that at turn-on

the PD not exceed the inrush current limit for more than

50ms. The LTC4267-1 is not restricted to the 50ms time

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