LTC4306 datasheet(4/20 Pages) LINER

4 / 20 page

LTC4306

4306f

The

● denotes specifications which apply over the full specified temperature

range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: Guaranteed by design and not subject to test.

Note 3: The boosted pull-up currents are regulated to prevent excessively

fast edges for light loads. See the Typical Performance Characteristics for

rise time as a function of VCC and parasitic bus capacitance CBUS and for

IBOOST as a function of VCC and temperature.

Note 4: When a logic low voltage, VLOW, is forced on one side of the

Upstream-Downstream Buffers, the voltage on the other side is regulated

to a voltage VLOW2 = VLOW + VOS, where VOS is a positive offset voltage.

VOS,UP-BUF is the offset voltage when the LTC4306 is driving the upstream

pin (e.g., SDAIN) and VOS,DOWN-BUF is the offset voltage when the

LTC4306 is driving the downstream pin (e.g., SDA1). See the Typical

Performance Characteristics for VOS,UP-BUF and VOS,DOWN-BUF as a

function of VCC and bus pull-up current.

Note 5: When floating, the ADR0-ADR2 pins can tolerate pin leakage

currents up to IADR(FLOAT) and still convert the address correctly.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VALERT1-4(IN)

ALERT1-ALERT4 Pin Input Falling

●

0.8

1.0

1.2

Threshold Voltages

VALERT1-4(HY)

ALERT1-ALERT4 Pin Input Threshold

Hysteresis Voltages

I2C Interface

VADR(H)

ADR0-2 Input High Voltage

●

0.75 • VCC 0.9 • VCC

VADR(L)

ADR0-2 Input Low Voltage

●

0.1 • VCC 0.25 • VCC

IADR(IN, L)

ADR0-2 Logic Low Input Current

ADR0-2 = 0V, VCC = 5.5V

●

–30

–60

–80

µA

IADR(FLOAT)

ADRO-2 Allowed Input Current

VCC = 2.7V, 5.5V (Note 5)

●

±5

±13

µA

IADR(IN, H)

ADR0-2 Logic High Input Current

ADR0-2 = VCC = 5.5V

●

µA

VSDAIN,SCLIN(TH) SDAIN, SCLIN Input Falling Threshold

VCC = 5.5V

●

1.4

1.6

1.8

Voltages

VSDAIN,SCLIN(HY) SDAIN, SCLIN Hysteresis

ISDAIN,SCLIN(OH) SDAIN, SCLIN Input Current

SCL, SDA = VCC

●

±5

µA

CIN

SDA, SCL Input Capacitance

(Note 2)

VSDAIN(OL)

SDAIN Output Low Voltage

ISDA = 4mA, VCC = 2.7V

●

0.2

0.4

I2C Interface Timing

fSCL

Maximum SCL Clock Frequency

(Note 2)

400

kHz

tBUF

Bus Free Time Between Stop/Start Condition

(Note 2)

0.75

1.3

µs

tHD,STA

Hold Time After (Repeated) Start Condition

(Note 2)

100

tSU,STA

Repeated Start Condition Set-up Time

(Note 2)

–30

tSU,STO

Stop Condition Set-up Time

(Note 2)

–30

tHD,DATI

Data Hold Time Input

(Note 2)

–25

tHD,DATO

Data Hold Time Output

(Note 2)

300

600

900

tSU,DAT

Data Set-up Time

(Note 2)

100

SCL, SDA Fall Times

(Note 2)

20 + 0.1

•

300

CBUS

tSP

Pulse Width of Spikes Suppressed by the

(Note 2)

150

250

Input Filter

LTC4306 数据表(PDF) 4 Page - Linear Technology

LTC4306 数据表(HTML) 4 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载

链接网址

LTC4306 数据表(PDF) 4 Page - Linear Technology

LTC4306 数据表(HTML) 4 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表 下载

链接网址

数据表下载