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LTM4601/LTM4601-1

4601f

APPLICATIO S I FOR ATIO

Figure 16. 5V at 8A Design Without Differential Ampliﬁer

Solution

Lower the switching frequency at lower input voltages to

allow for higher duty cycles, and meet the 400ns mini-

mum off-time at 4.5V input voltage. The off-time should

be about 500ns with 100ns guard band. The duty cycle

for (3.3V/4.5) = ~73%. Frequency = (1 – DC)/tOFF, or

(1 – 0.73)/500ns = 540kHz. The switching frequency needs

to be lowered to 540kHz at 4.5V input. tON = DC/frequency,

or 1.35µs. The fSET pin voltage compliance is 1/3 of VIN, and

the IfSET current equates to 38µA with the internal 39.2k.

The IfSET current needs to be 24µA for 540kHz operation.

A resistor can be placed from VOUT to fSET to lower the

effective IfSET current out of the fSET pin to 24µA. The

fSET pin is 4.5V/3 =1.5V and VOUT = 3.3V, therefore 130k

will source 14µA into the fSET node and lower the IfSET

current to 24µA. This enables the 540kHz operation and

the 4.5V to 20V input operation for down converting to

3.3V output. The frequency will scale from 540kHz to 1.1

MHz over this input range. This provides for an effective

output current of 8A over the input range.

VOUT

VFB

MARG0

MARG1

VOUT_LCL

NC3

NC1

NC2

PGOOD

MPGM

RUN

COMP

INTVCC

DRVCC

TRACK/SS

PLLIN

LTM4601-1

392k

RfSET

100k

RSET

8.25k

100

µF

6.3V

SANYO POSCAP

4601 F16

VOUT

TRACK/SS CONTROL

REVIEW TEMPERATURE

DERATING CURVE

C6 100pF

REFER TO

TABLE 2

µF

25V

IMPROVE

EFFICIENCY

FOR

≥12V INPUT

µF

25V

100k

VIN

VOUT

fSET

PGND

MARGIN CONTROL

SGND

5% MARGIN

VIN

10V TO 20V

DUAL

CMSSH-3C3

SOT-323

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