LTC2053/LTC2053-SYNC

11

2053syncfb

–

+

–

+

EXTERNAL

CLOCK

3

2053 F02

8

5V

4

5

1

6 R2

1kΩ

R1

7

2

LTC2053-SYNC

CLK

5V

4.7nF

0V

0

12

10

8

6

4

2

0

2000

4000

6000

8000

2053 F05

10000

Typ LTC2053 Sample Frequency

Noise in 10Hz Bandwidth

APPLICATIO S I FOR ATIO

The LTC2053-SYNC is tested with a sample clock of 3kHz

In addition the LTC2053-SYNC is tested at 1/2 and 2X this

frequency to verify proper operation. The curves in the

Typical Performance Characteristics section of this

datasheet apply to the LTC2053-SYNC when driving it with

rate). Below are three curves that show the behavior of the

LTC2053-SYNC as the clock frequency is varied. The

offset is essentially unaffected over a 2:1 increase or

decrease of the typical LTC2053 sample clock speed. The

bias current is directly proportional to the clock speed. The

noise is roughly proportional to the square root of the

clock frequency. For optimum noise and bias current

performance, drive the LTC2053-SYNC with a nominal

24kHz external clock (3kHz sample clock).

Synchronizing to an External Clock

(LTC2053-SYNC Only)

The LTC2053 has an internally generated sample clock

that is typically 3kHz. There is no need to provide the

LTC2053 with a clock. However, in some applications, it

may be desirable for the user to control the sampling

frequency more precisely to avoid undesirable aliasing.

This can be done with the LTC2053-SYNC. This device

uses PIN 1 as a clock input whereas the LTC2053 uses Pin

1 as an enable pin. If CLK (PIN 1) is left floating on the

LTC2053-SYNC, the device will run on its internal oscilla-

tor, similar to the LTC2053. However, if not externally

synchronizing to a system clock, it is recommended that

the LTC2053 be used instead of the LTC2053-SYNC

because the LTC2053-SYNC is sensitive to parasitic ca-

pacitance on the CLK pin when left floating. Clocking the

LTC2053-SYNC is accomplished by driving the CLK pin

at 8 times the desired sample clock frequency. This

completely disables the internal clock. For example, to

achieve the nominal LTC2053 sample clock rate of 3kHz,

a 24kHz external clock should be applied to the CLK pin

of the LTC2053-SYNC. If a square wave is used to drive the

CLK pin, a 5µs RC time constant should be placed in front

of the CLK pin to maintain low offset voltage performance

(see Figure 2). This avoids internal and external coupling

of the high frequency components of the external clock at

the instant the LTC2053-SYNC holds the sampled input.

LTC2053-SYNC

Input Offset

vs Sample Frequency

LTC2053-SYNC

Average Input Bias Current

vs Sample Frequency

LTC2053-SYNC

Input Referred Noise

vs Sample Frequency

0

20

15

10

5

0

–5

–10

–15

–20

2000

4000

6000

8000

2053 F03

10000

Typ LTC2053 Sample Frequency

0

14

12

10

8

6

4

2

0

2000

4000

6000

8000

2053 F04

10000

Typ LTC2053 Sample Frequency

Figure 2