LTC2248 datasheet(18/24 Pages) LINER

18 / 24 page

LTC2248/LTC2247/LTC2246

224876fa

APPLICATIO S I FOR ATIO

bearing on how much SNR degradation will be experi-

enced. For high crest factor signals such as WCDMA or

OFDM, where the nominal power level must be at least 6dB

to 8dB below full scale, the use of these translators will

have a lesser impact.

The transformer in the example may be terminated with

the appropriate termination for the signaling in use. The

use of a transformer with a 1:4 impedance ratio may be

desirable in cases where lower voltage differential signals

are considered. The center tap may be bypassed to ground

through a capacitor close to the ADC if the differential

signals originate on a different plane. The use of a capaci-

tor at the input may result in peaking, and depending on

transmission line length may require a 10

Ω to 20Ω ohm

series resistor to act as both a low pass filter for high

frequency noise that may be induced into the clock line by

neighboring digital signals, as well as a damping mecha-

nism for reflections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2248/LTC2247/

LTC2246 is 65Msps (LTC2248), 40Msps (LTC2247), and

25Msps (LTC2246). For the ADC to operate properly, the

CLK signal should have a 50% (

±5%) duty cycle. Each half

cycle must have at least 7.3ns (LTC2248), 11.8ns

(LTC2247), and 18.9ns (LTC2246) for the ADC internal

circuitry to have enough settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the CLK pin to sample the analog

input. The falling edge of CLK is ignored and the internal

falling edge is generated by a phase-locked loop. The input

clock duty cycle can vary from 40% to 60% and the clock

duty cycle stabilizer will maintain a constant 50% internal

duty cycle. If the clock is turned off for a long period of

time, the duty cycle stabilizer circuit will require a hundred

clock cycles for the PLL to lock onto the input clock. To use

the clock duty cycle stabilizer, the MODE pin should be

connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2248/LTC2247/LTC2246 sample

rate is determined by droop of the sample-and-hold cir-

cuits. The pipelined architecture of this ADC relies on

Figure 14. Digital Output Buffer

LTC2248/47/46

224876 F12

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

D13 – D0

(2V Range)

(Offset Binary)

(2’s Complement)

>+1.000000V

11 1111 1111 1111

01 1111 1111 1111

+0.999878V

11 1111 1111 1111

01 1111 1111 1111

+0.999756V

11 1111 1111 1110

01 1111 1111 1110

+0.000122V

10 0000 0000 0001

00 0000 0000 0001

0.000000V

10 0000 0000 0000

00 0000 0000 0000

–0.000122V

01 1111 1111 1111

11 1111 1111 1111

–0.000244V

01 1111 1111 1110

11 1111 1111 1110

–0.999878V

00 0000 0000 0001

10 0000 0000 0001

–1.000000V

00 0000 0000 0000

10 0000 0000 0000

<–1.000000V

00 0000 0000 0000

10 0000 0000 0000

storing analog signals on small valued capacitors. Junc-

tion leakage will discharge the capacitors. The specified

minimum operating frequency for the LTC2248/LTC2247/

LTC2246 is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overflow bit.

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50

Ω to external

circuitry and may eliminate the need for external damping

resistors.

LTC2248 数据表(PDF) 18 Page - Linear Technology

LTC2248 数据表(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载

链接网址

LTC2248 数据表(PDF) 18 Page - Linear Technology

LTC2248 数据表(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表 下载

链接网址

数据表下载