54ACT16652, 74ACT16652

16-BIT TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCAS128C – MARCH 1990 – REVISED APRIL 1996

2

POST OFFICE BOX 655303

description (continued)

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the

appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable

inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the

internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output

reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each

set of bus lines remains at its last state.

The 74ACT16652 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and

functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16652 is characterized for operation over the full military temperature range of –55

°C to 125°C. The

74ACT16652 is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

INPUTS

DATA I/O†

OPERATION OR FUNCTION

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1–A8

B1–B8

OPERATION OR FUNCTION

L

H

L

L

X

X

Input

Input

Isolation

L

H

↑↑

X

X

Input

Input

Store A and B data

X

H

↑

L

X

X

Input

Unspecified‡

Store A, hold B

H

H

↑↑

X‡

X

Input

Output

Store A in both registers

L

X

L

↑

X

X

Unspecified‡

Input

Hold A, store B

L

L

↑↑

XX‡

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

L

X

H

X

Input

Output

Stored A data to B bus

H

L

L

L

H

H

Output

Output

Stored A data to B bus and

stored B data to A bus

† The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always

enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡ Select control = L; clocks can occur simultaneously.

Select control = H; clocks must be staggered to load both registers.