CD54ACT161, CD74ACT161

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS298B – APRIL 2000 – REVISED MARCH 2003

5

POST OFFICE BOX 655303

typical clear, preset, count, and inhibit sequence

The following sequence is illustrated below:

1.

Clear outputs to zero (asynchronous)

2.

Preset to binary 12

3.

Count to 13, 14, 15, 0, 1, and 2

4.

Inhibit

Data

Inputs

Data

Outputs

CLR

LOAD

A

B

C

D

CLK

ENP

ENT

RCO

QA

QB

QC

QD

Async

Clear

Preset

Count

Inhibit

12

13

14

15

0

1

2