2

Functional Diagram

IEC Logic Symbol

TRUTH TABLE (Note 1)

INPUTS

OUTPUTS

RESET MR

CLOCK CP

DATA Dn

Qn

LX

XL

H

↑

HH

H

↑

LL

HL

X

Q0

NOTE:

1. H = HIGH Voltage Level (Steady State)

L = LOW Voltage Level (Steady State)

X = Irrelevant

↑ = Transition from low to high level.

Q0 = The level of Q before the indicated steady state input conditions were established.

11

3

4

7

8

13

14

17

2

5

6

9

12

15

16

18

GND = PIN 10

1

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

D0

D1

D2

D3

D4

D5

D6

D7

CLOCK

CP

RESET MR

DATA OUTPUTS

DATA INPUTS

CD74FCT273

2

5

6

9

R

1

3

4

7

8

12

15

16

19

13

14

17

18

>C1

11

1D

CD74FCT273