2

Functional Diagram

TRUTH TABLE

INPUTS

INTERNAL

Q STATES

OUTPUT

Q7

MASTER

RESET

PARALLEL

ENABLE

CLOCK

ENABLE

CLOCK

SERIAL

PARALLEL

D0 D7

Q0

Q1

LX

X

X

X

X

L

L

L

H

X

L

L

X

X

Q00

Q10

Q0

HL

L

↑

X

a...h

a

b

h

HH

L

↑

H

X

H

Q0n

Q6n

HH

L

↑

L

X

L

Q0n

Q6n

HXH

↑

X

X

Q00

Q10

Q70

H= High Voltage Level

L= Low Voltage Level

X= Don’t Care

↑= Transition from Low to High Level

a...h = The level of steady-state input at inputs D0 thru D7, respectively.

Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.

Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent

↑ transition of the clock.

8 - REGISTERS

PARALLEL ENABLE CIRCUIT

D0 D1 D2 D3 D4 D5 D6 D7

PE

CP

CE

MR

D0

D7

Q7

CD54HC166, CD74HC166, CD54HCT166, CD74HCT166