CD74HC7046AM datasheet(21/26 Pages) TI

21 / 26 page

Lock Detector Circuit

The lock detector feature is very useful in data synchroniza-

tion, motor speed control, and demodulation. By adjusting

the value of the lock detector capacitor so that the lock out-

put will change slightly before actually losing lock, the

designer can create an “early warning” indication allowing

corrective measures to be implemented. The reverse is also

true, especially with motor speed controls, generators, and

clutches that must be set up before actual lock occurs or dis-

connected during loss of lock.

When using phase comparator 1, the detector will only indi-

cate a lock condition on the fundamental frequency and not

on the harmonics, which PC1 will lock on.

PLL Conditions with

No Signal at the

SIGIN Input

PC1

VCO adjusts to fo with φDEMOUT = 90

o and V

VCOIN = 1/2 VCC (see Figure 2)

PC2

VCO adjusts to fMIN with φDEMOUT = -360

o and V

VCOIN = 0V (see Figure 4)

PLL Frequency

Capture Range

PC1 or PC2

Loop Filter Component Selection

PLL Locks on

Harmonics at Center

Frequency

PC1

Yes

PC2

Noise Rejection at

Signal Input

PC1

High

PC2

Low

AC Ripple Content

when PLL is Locked

PC1

fr = 2fi, large ripple content at φDEMOUT = 90

PC2

fr = fi, small ripple content at φDEMOUT = 0

SUBJECT

PHASE

COMPARATOR

DESIGN CONSIDERATIONS

A small capture range (2fc) is obtained if τ > 2fc ≈ (1/π) (2πfL/τ1.)

1/2

FIGURE 48. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET

(A)

τ1 = R3 x C2

(B) AMPLITUDE CHARACTERISTIC

INPUT

OUTPUT

|F(j

ω)|

-1/

FIGURE 49. SIMPLE LOOP FILTER FOR PLL WITH OFFSET

(A)

τ2 = R4 x C2;

(B) AMPLITUDE CHARACTERISTIC

|F(j

ω)|

-1/

τ2

INPUT

OUTPUT

τ3 = (R3 + R4) x C2

-1/

τ3

τ3 1/τ2

m =

R3 + R4

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