CDC111

1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER

SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999

1

POST OFFICE BOX 655303

Applications

(LVPECL)-Compatible Inputs and Outputs

Differential Clock Outputs

Distribution From a Single-Ended Clock

Input

Enable

description

The differential LVPECL clock-driver circuit

distributes one pair of differential LVPECL clock

inputs (CLKIN, CLKIN) to nine pairs of differential

clock (Y, Y) outputs with minimum skew for clock

distribution. It is specifically designed for driving

50-

Ω transmission lines.

When the output-enable (OE) is low, the nine differential outputs switch at the same frequency as the differential

clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state,

Y outputs are in the high state).

The CDC111 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

CLKIN

CLKIN

OE

Yn

Yn

X

X

H

L

H

L

HL

L

H

H

LL

H

L

L

VREF

LL

H

H

VREF

LH

L

VREF

LL

H

L

VREF

H

L

L

H

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

32 1

13 14

5

6

7

8

9

10

11

Y0

Y0

Y1

Y1

Y2

Y2

Y8

Y8

Y7

Y7

Y6

Y6

4

15 16 17 18

28 27 26

25

24

23

22

21

20

19

12

FN PACKAGE

(TOP VIEW)

NC – No internal connection