CDC2510C

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS621 – DECEMBER 1998

7

POST OFFICE BOX 655303

TYPICAL CHARACTERISTICS

0

5

10

15

20

25

30

35

40

45

50

C(LF) – Lumped Feedback Capacitance at FBIN – pF

10

0

–10

–20

20

–30

–40

100

0

–300

200

–400

Phase Error

Phase Adjustment Slope

–100

–200

CDC2510C

PHASE ADJUSTMENT SLOPE AND PHASE ERROR

vs

LOAD CAPACITANCE

VCC = 3.3 V

fc = 100 MHz

C(LY) = 30pF

TA = 25°C

See Notes A and B

Figure 3

0

5

10

15

20

25

30

35

40

45

50

C(LF) – Lumped Feedback Capacitance at FBIN – pF

0

–10

–20

–30

10

–40

–50

0

–100

–400

100

–500

Phase Error

Phase

Adjustment Slope

–200

–300

CDC2510A

PHASE ADJUSTMENT SLOPE AND PHASE ERROR

vs

LOAD CAPACITANCE

VCC = 3.3 V

fc = 100 MHz

C(LY) = 30pF

TA = 25°C

See Notes A and B

Figure 4

NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω Phase error measured from CLK to Y

B. CLF = Lumped feedback capacitance at FBIN