CDC2536

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS377D – APRIL 1994 – REVISED OCTOBER 1998

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POST OFFICE BOX 655303

and Clock-Generation Applications

to Operate at One-Half or Double the Input

Frequency

Synchronize the Outputs to the Clock Input

High-Speed Microprocessor

Transmission Lines

Significantly Reduces Power Dissipation

Switching Noise

Small-Outline Package

description

The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to

precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is

specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from

50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536

series-damping resistors, eliminating the need for external termination components.

The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock

(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between

CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL)

input configures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin

is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the

duty cycle at the input clock.

Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.

When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass

the PLL. TEST should be strapped to GND for normal operation.

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC-

ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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AGND

CLKIN

SEL

OE

GND

1Y1

GND

1Y2

GND

1Y3

AGND

FBIN

TEST

CLR

2Y1

GND

2Y2

GND

2Y3

GND

DB PACKAGE

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