CDC921

133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS

WITH 3-STATE OUTPUTS

SCAS623 –MAY 27, 1999

15

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

tsk(o)

VT_REF

CPUx or PCIx Clock

3V66 or CPUx

CPUx or PCIx Clock

VT_REF

VT_REF

t(low)

t(high)

tc

t

t

PLH

–t

PHL

Duty Cycle

+

t

(low)

100

VT_REF

t(off) [3V66 to PCIx]

t(off) [CPUx to APIC]

t(off) [CPUx to 3V66]

3V66, PCIx, or APIC

Figure 4. Waveforms for Calculation of Skew, Offset, and Jitter

CPU

(internal)

PCI

(internal)

PWR_DWN

PCI

(external)

CPU

(external)

VCO

CRYSTAL

NOTE A: Shaded sections on the VCO and Crystal waveforms indicate that the VCO and crystal oscillators are active and there is a valid clock.

Figure 5. Power-Down Timing