Dual 8-Bit Parity Generator/Checker

CY54/74FCT480T

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

SCCS025 - May 1993 - Revised March 2000

Copyright

1CY54/74FCT480T

Features

• Function, pinout and drive compatible with FCT and F

logic

• FCT-A speed at 7.5 ns max. (Com’l)

FCT-B speed at 5.6 ns max. (Com’l)

FCT functions

• Edge-rate control circuitry for significantly improved

noise characteristics

• Power-off disable feature

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Sink Current

64 mA (Com’l),

32 mA (Mil)

Source Current

32 mA (Com’l),

12 mA (Mil)

• Two 8-bit parity generator/checkers

• Open drain Active LOW parity error output

• Expandable for larger word widths

Functional Description

The

FCT480T

is

a

high-speed

dual

8-bit

parity

generator/checker. Each parity generator/checker accepts

eight data bits and one parity bit as inputs, and generates a

sum and parity error output. The FCT480T can be used in

ODD parity systems. The parity error output is open-drain,

designed for easy expansion of the word width by a wired-OR

connection of several FCT480T type devices. Since additional

logic is not needed, the parity generation or checking times

remain the same as for an individual FCT480T device.

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

Logic Block Diagram

Pin Configurations

FCT480T–1

28

4

5

6

7

8

9

10

3

2

1

27

13

14

15

16

17

26

25

24

23

22

21

20

11

12

19

18

LCC

Top View

CHK/GEN

NC

ERROR

NC

GND

CHK/GEN

ERR

FCT480T–2

1

2

3

4

5

6

7

8

9

10

11

12

16

17

18

19

20

24

23

22

21

13

14

CHK/GEN

GND

ERROR

FCT480T–3

15

DIP/SOIC/QSOP

Top View